The present invention relates to a differential amplifier circuit, and more particularly, to a variable transconductance circuit formed on a semiconductor integrated circuit, and an optical disk device having such a variable transconductance circuit placed on a signal processing path.
A conventional transconductance circuit disclosed in Japanese Laid-Open Patent Publication No. 11-68477 will be described with reference to FIG. 15.
MOS transistors M50 and M51 constitute an input differential pair biased with a current Io. When a voltage signal Vi is input, MOS transistors M56 and M57 respectively drive gate voltages of MOS transistors M52 and M53 so that the gate-source voltages thereof are constant. At this time, the input voltage signal Vi is converted to a current ΔI1 with a resistance R connected between the sources of the MOS transistors M50 and M51, and the current ΔI1 flows to the MOS transistors M52 and M53. This relationship is represented by Expression (1) below. The current ΔI1 is output from the drains of MOS transistors M54 and M55.
                              Δ          ⁢                                          ⁢          I          ⁢                                          ⁢          1                =                  Vi          R                                    (        1        )            
The output current ΔI1 is input into the drains of MOS transistors M58 and M59. The gate and drain of each of the MOS transistors M58 and M59 are connected to each other via a resistance Rg, and the gates thereof are common-connected. At this time, since the equal current flows to the MOS transistors M58 and M59, the current ΔI1 of Expression (1) flows to the resistances Rg, generating a voltage (V+-V−) at both ends of the resistances Rg. With this voltage (V+-V−), the gates of MOS transistors M60 and M61 are driven. A drain current difference ΔI2 between the MOS transistors M60 and M61 at this time is represented by Expression (2):
                                                                        Δ                ⁢                                                                  ⁢                I                ⁢                                                                  ⁢                2                            =                            ⁢                              k                ⁢                                                                  ⁢                                  β                  ⁡                                      [                                                                                            (                                                                                    V                              +                                                        -                            Vth                                                    )                                                2                                            -                                                                        (                                                                                    V                              -                                                        -                            Vth                                                    )                                                2                                                              ]                                                                                                                                          =                                ⁢                                  4                  ⁢                                                                          ⁢                  k                  ⁢                                                                                    β                        ·                        Io                                                              ·                    Rg                                                              ⁣                                                ·                  Δ                                ⁢                                                                  ⁢                I                ⁢                                                                  ⁢                1                                                                                        =                            ⁢                              4                ⁢                                                                  ⁢                k                ⁢                                                                            β                      ·                      Io                                                        ·                                      Rg                    R                                    ·                  Vi                                                                                        (        2        )            where β=charge mobility×capacity of gate oxide film/2, k=(transistor size of MOS transistors M60 and M61)/(transistor size of MOS transistors M58 and M59), and Vth is a transistor threshold voltage.
From Expression (2), the transconductance (gm) is represented by Expression (3):
                    gm        =                  4          ⁢          k          ⁢                                                    β                ·                Io                                      ·                          Rg              R                                                          (        3        )            which indicates that gm is allowed to vary sequentially by varying Io.
Gm is proportional to the square root of lo according to Expression (3). Therefore, to allow gm to vary up to 10 times its minimum value, it is necessary to vary Io up to 100 times its minimum value. In general, the gate-source voltage Vgs and the operating current Io of a MOS transistor have a relationship (Vgs-Vth) ∝√{square root over ( )}Io, in which if lo is increased by 100 times, Vgs-Vth will increase by 10 times. Since Vgs-Vth must be about 0.2 V at minimum to operate the MOS transistor in the saturation region, Vgs-Vth will be 2V at maximum. Low power supply voltage operation is therefore difficult, and also the 100-fold current variation will increase current consumption. Thus, wide-range gm variation and low power consumption are in a trade-off relationship.
To solve the problem described above, Japanese Laid-Open Patent Publication No. 2001-292051 discloses a configuration of connecting a plurality of transconductors in parallel to enable wide-range gm variation and low power supply voltage operation. However, this configuration still has problems in current consumption and on-board circuit area.
In optical disk devices such as DVDs, for example, a filter circuit used for signal processing must respond to a wide range of signals including a high-speed signal about 100 times as fast as the lowest-speed signal. Also, a variable gain amplifier, which normalizes a variation in signal amplitude caused by a medium and an optical pickup before performing signal processing, is required to provide a wide range of gains including a gain 10 to 20 times as large as the smallest gain. To achieve such a filter circuit and variable gain amplifier, a variable gm circuit serves as an important component. However, with a power supply voltage as low as just about 3V, the conventional variable gm circuit can only secure a variable range up to about five times the gm lowest value for one circuit. Therefore, a plurality of such variable gm circuits are connected in parallel or in series to achieve a filter circuit and variable gain amplifier. This causes the problems of increase in power consumption and on-board circuit area.